1. Field of the Invention
The present invention relates to an oversampling circuit and an oversampling method that are used for a receiver, etc., capable of high-speed serial communication, such as Serial-ATA and PCI Express.
2. Description of the Related Art
A demand for large-capacity and high-speed data transmission between devices, boards, and chips has been increasing recently. To meet the demand, a so-called high-speed serial transmission method has been adopted more frequently as a transmission interface standard. According to the method, a clock having the same frequency as that of transmission data is embedded in the transmission data (embedded clock), and the clock is extracted from the data received at a data receiving unit to recover the received data on the basis of the extracted clock. A circuit carrying out recovery of the clock and data is called a clock data recovery circuit (CDR circuit), which is usually provided as a PLL (Phase Locked Loop) circuit. The PLL circuit makes control to synchronize an inner clock generated by a VCO (Voltage Control Oscillator) included in the PLL circuit with the phase of a received signal.
Nowadays, however, high-speed serial transmission pushes faster clock frequencies, leading to a demand for a clock frequency of several GHz. This invites such problems as increasing chip size in a PLL circuit, greater power consumption, raising cots, more complicated circuit design and layout, etc. In addition, the higher a clock frequency becomes, the smaller a PLL jitter tolerance. This brings the necessity that a clock used for data reception must synchronize with input data at an extremely precise level, which is very difficult work to do.
An oversampling type clock data recovery circuit has been suggested as a solution to the above problem, and is now in popular use. This clock data recovery circuit generates multiphase clock signals out of a reference clock by shifting the phase of the reference clock at equal intervals, samples input data at respective phases to obtain a bit string to detect timing of logic inversion from the bit string, and reproduces the clock and data on the basis of a detection result. This allows a circuit configuration dominantly composed of digital circuits except a multiphase clock generating unit, which circuit configuration is easy to achieve.
The multiphase clocks used in the above circuit configuration, however, pose a problem of phase differences between generated clocks. If the phase differences are not equal intervals, the recovered clock comes to have a shorter cycle, which could cause malfunction if worst comes to worst.
To solve such a problem, the inventor has suggested a data recovery method and a data recovery circuit.
According to the data recovery method and data recovery circuit, a clock included in input data is not recovered, but oversampling of the input data is carried out using multiphase clocks that have frequencies equal to or lower than the frequency of the clock and that are independent of the input signal, and the input data is recovered exactly by using the result of oversampling (e.g., see Japanese Patent Application Laid-Open No. 2005-192192).
The above method, however, is carried out on the assumption that the phase differences between the multiphase clocks are equal intervals. If the phase differences are not equal intervals, a resulting error gives an observation of an increase in the jitter of a reception signal, leading to the deterioration of reception characteristics.
Usually, a PLL circuit or a DLL (Delay Lock Loop) circuit is used to generate the phases of multiphase clocks necessary for oversampling. Both circuits are provided as a circuit constructed by connecting buffers circularly, such as a multiphase clock circuit shown in FIG. 31.
The circuit shown in FIG. 31 represents a case where four-phase clocks are generated using two differential amplifiers 51a and 51b, in which case the number of buffer stages and the overall configuration vary properly according to the number of clock phases required. In FIG. 31, generated multiphase clocks are denoted by CLK0 to CLK3. In generating the multiphase clocks, the circuits of the differential amplifiers 51a and 51b and load capacitances attached to wiring. etc., are designed to be identical so that every risetime and falltime of the clocks becomes identical at the differential amplifiers 51a and 51b, respectively.
In actual operation, however, devices mounted on the same chip show locally dispersed characteristics, and load capacities attached to wiring vary depending on the surrounding circuit, so that making phases completely uniform is difficult. Besides, as a frequency gets higher, an allowable error between the phases of multiphase clocks gets smaller, which increases current required by the differential amplifiers 51a and 51b used for clock generation, leading to a tendency of an increase in switching current. As a result, power voltage for the differential amplifiers fluctuates locally, thus the characteristics of each buffer stage fluctuate variously.
An effective means for knowing power fluctuation at a design stage is yet to be established. Reducing the phase dispersion between multiphase clocks to a size within a desirable error, therefore, is extremely difficult. When the risetimes and falltimes of respective clocks are uniform, multiphase clocks with phase differences of equal intervals can be generated, as shown in a timing chart shown in FIG. 32A. When the characteristics of respective buffers are dispersed as described above, however, the phase differences between the multiphase clocks are not formed as the equal interval.
To solve this problem, a clock and data recovery circuit and a clock control method for the same have been suggested (e.g., see Japanese Patent No. 3636657). According to this circuit and method, phase interpolators are used at a multiphase clock generating unit to carry out phase adjustment.
A phase adjusting circuit of Japanese Patent No. 3636657, however, puts out clocks having phases internally divided by the interpolators on the basis of multiphase clocks originally having phase differences of equal interval. When the phases of the original multiphase clocks are shifted, therefore, the phase adjustment does not have any significance. Besides, the interpolators are used in the number same as that of the phases of the clocks, and these interpolators show different delay times due to variations in device characteristics, local power voltage fluctuation, etc. Achieving completely identical phases, therefore, is difficult.
A phase shift quantity detecting circuit for multiphase clocks and a bit synchronous circuit using the phase shift quantity detecting circuit have been suggested (e.g., see Japanese Patent No. 3414700). According to the phase shift quantity detecting circuit and the bit synchronous circuit, multiphase clocks having phase differences of virtually equal intervals are generated on the basis of a reference clock, and each of the multiphase clocks is sampled using the reference clock to detect a phase shift quantity so that the phase shift quantity (delay quantity) of the multiphase clocks is corrected into a proper value.
The phase shift quantity detecting circuit of Japanese Patent No. 3414700 is provided on the assumption that a plurality of delay circuits incorporated in the detecting circuit has virtually equal delay characteristics. For the reason as described above, however, delay characteristics are dispersed, which brings difficulty in generating multiphase clocks having phase differences of equal intervals. Besides, the phase shift quantity detecting circuit compares edges of a clock with that of another clock. This makes exact detection of phases difficult as clock frequencies get higher.